256k x 4 static ram cy7c106bn cy7c1006bn cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-06429 rev. ** revised february 1, 2006 features ?high speed ?t aa = 15 ns ? cmos for optimum speed/power ? low active power ?495 mw ? low standby power ?275 mw ? 2.0v data retention (optional) ? automatic power-down when deselected ? ttl-compatible inputs and outputs functional description the cy7c106bn and cy7c1006bn are high-performance cmos static rams organized as 262,144 words by 4 bits. easy memory expansion is provided by an active low chip enable (ce ), an active low output enable (oe ), and three-state drivers. these devices have an automatic power-down feature that reduces power consumption by more than 65% when the devices are deselected. writing to the devices is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. data on the four i/o pins (i/o 0 through i/o 3 ) is then written into the location specified on the address pins (a 0 through a 17 ). reading from the devices is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing write enable (we ) high. under these conditions, the contents of the memory location specified by the address pins will appear on the four i/o pins. the four input/output pins (i/o 0 through i/o 3 ) are placed in a high-impedance state when the devices are deselected (ce high), the outputs are disabled (oe high), or during a write operation (ce and we low). the cy7c106bn is available in a standard 400-mil-wide soj; the cy7c1006bn is available in a standard 300-mil-wide soj. logic block diagram pin configuration 512 x 512 x 4 array a 1 a 0 a 10 a 12 a 11 a 13 a 14 column decoder row decoder sense amps power down oe input buffer a 15 a 16 a 17 1 2 3 4 5 6 7 8 9 10 11 14 15 16 20 19 18 17 21 24 23 22 top view soj 12 13 25 28 27 26 gnd a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 17 v cc a 16 a 15 a 14 a 13 i/o 3 i/o 2 i/o 1 i/o 0 a 9 a 0 a 10 ce oe nc a 12 a 11 we we ce i/o 0 i/o 1 i/o 2 i/o 3 a 2 a 3 a 4 a 6 a 7 a 8 a 9 a 5 [+] feedback [+] feedback
cy7c106bn cy7c1006bn document #: 001-06429 rev. ** page 2 of 8 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................?65c to +150c ambient temperature with power applied......................... ...................?55c to +125c supply voltage on v cc relative to gnd [1] .... ?0.5v to +7.0v dc voltage applied to outputs in high z state [1] ....................................?0.5v to v cc + 0.5v dc input voltage [1] .................................?0.5v to v cc + 0.5v current into outputs (low).... ..................................... 20 ma static discharge voltage ........ .............. .............. ....... >2001v (per mil-std-883, method 3015) latch-up current ..................................................... >200 ma selection guide 7c106bn-15 7c1006bn-15 7c106bn-20 7c1006bn-20 maximum access time (ns) 15 20 maximum operating current (ma) 80 75 maximum standby current (ma) 30 30 operating range range ambient temperature [2] v cc commercial 0c to +70c 5v 10% industrial ?45c to +85c electrical characteristics over the operating range parameter description test conditions 7c106bn-15 7c1006bn-15 7c106bn-20 7c1006bn-20 min. max. min. max. unit v oh output high voltage v cc = min., i oh = ?4.0 ma 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 v v ih input high voltage 2.2 v cc + 0.3 2.2 v cc + 0.3 v v il input low voltage [1] ?0.3 0.8 ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 ?1 +1 ma i oz output leakage current gnd < v i < v cc , output disabled ?5 +5 ?5 +5 ma i os output short circuit current [3] v cc = max., v out = gnd ?300 ?300 ma i cc v cc operating supply current v cc = max., i out = 0 ma, f = f max = 1/t rc 80 75 ma i sb1 automatic ce power-down current ?ttl inputs max. v cc , ce > v ih , v in > v ih or v in < v il , f = f max 30 30 ma i sb2 automatic ce power-down current ?cmos inputs max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v or v in < 0.3v, f=0 com?l 10 10 ma capacitance [4] parameter description test conditions max. unit c in : addresses input capacitance t a = 25c, f = 1 mhz, v cc = 5.0v 7pf c in : controls 10 pf c out output capacitance 10 pf notes: 1. v il (min.) = ?2.0v for pulse durations of less than 20 ns. 2. t a is the ?instant on? case temperature. 3. not more than 1 output should be shorted at one time. dura tion of the short circuit shou ld not exceed 30 seconds. 4. tested initially and after any design or process changes that may affect these parameters. [+] feedback [+] feedback
cy7c106bn cy7c1006bn document #: 001-06429 rev. ** page 3 of 8 ac test loads and waveforms switching characteristics over the operating range [5] 7c106b-15 7c1006b-15 7c106b-20 7c1006b-20 parameter description min. max. min. max. unit read cycle t rc read cycle time 15 20 ns t aa address to data valid 15 20 ns t oha data hold from address change 3 3 ns t ace ce low to data valid 15 20 ns t doe oe low to data valid 7 8 ns t lzoe oe low to low z 0 0 ns t hzoe oe high to high z [6, 7] 78ns t lzce ce low to low z [7] 33ns t hzce ce high to high z [6, 7] 78ns t pu ce low to power-up 0 0 ns t pd ce high to power-down 15 20 ns write cycle [8, 9] t wc write cycle time 15 20 ns t sce ce low to write end 12 15 ns t aw address set-up to write end 12 15 ns t ha address hold from write end 0 0 ns t sa address set-up to write start 0 0 ns t pwe we pulse width 12 15 ns t sd data set-up to write end 8 10 ns t hd data hold from write end 0 0 ns t lzwe we high to low z [7] 33ns t hzwe we low to high z [6, 7] 78ns notes: 5. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh and 30?pf load capacitance. 6. t hzoe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is measured 500 mv from steady-stat e voltage. 7. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 8. the internal write time of the memory is defined by the overlap of ce and we low. ce and we must be low to initiate a write, and the transition of either of these signals can terminate the write. the input data set-up and hold timing should be referenced to the leading edge of the si gnal that terminates the write. 9. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd . 90% 10% 3.0v gnd 90% 10% all input pulses 5v output 30 pf including jig and scope 5v output 5 pf including jig and scope (a) (b) output r1 480 ? r1 480 ? r2 255 ? r2 255 ? 167 ? equivalent to: th venin equivalent 1.73v rise time < 1v/ns fall time < 1v/n s [+] feedback [+] feedback
cy7c106bn cy7c1006bn document #: 001-06429 rev. ** page 4 of 8 data retention characteristics over the operating range parameter description conditions [10] min. max. unit v dr v cc for data retention 2.0 v i ccdr data retention current v cc = v dr = 2.0v, ce > v cc ? 0.3v, v in > v cc ? 0.3v or v in < 0.3v 250 a t cdr [4] chip deselect to data retention time 0 ns t r [4] operation recovery time 200 ms data retention waveform 4.5v 4.5v ce v cc t cdr v dr > 2v data retention mode t r switching waveforms read cycle no.1 [11, 12] read cycle no. 2 (oe controlled) [12, 13] notes: 10. no input may exceed v cc +0.5v. 11. device is continuously selected, oe and ce = v il . 12. we is high for read cycle. 13. address valid prior to or coincident with ce transition low. 1 previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance impedance i cc i sb t hzoe t hzce t pd high address ce data out v cc supply current oe [+] feedback [+] feedback
cy7c106bn cy7c1006bn document #: 001-06429 rev. ** page 5 of 8 write cycle no. 1 (ce controlled) [14, 15] write cycle no. 2 (we controlled, oe high during write) [14, 15] notes: 14. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. 15. data i/o is high impedance if oe = v ih . switching waveforms (continued) t wc data valid t aw t sa t pwe t ha t hd t sd t sce address ce data i/o we data valid t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe address ce we data i/o oe [+] feedback [+] feedback
cy7c106bn cy7c1006bn document #: 001-06429 rev. ** page 6 of 8 write cycle no. 3 (we controlled, oe low) [9, 15] switching waveforms (continued) data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe address ce we data i/o truth table ce oe we input/output mode power h x x high z power-down standby (i sb ) l l h data out read active (i cc ) l x l data in write active (i cc ) l h h high z selected, outputs disabled active (i cc ) ordering information speed (ns) ordering code package diagram package type operating range 15 cy7c106bn-15vc 51-85032 28-lead (400-mil) molded soj commercial cy7c1006bn-15vc 51-85031 28-lead (300-mil) molded soj 20 CY7C106BN-20VC 51-85032 28-lead (400-mil) molded soj commercial please contact local sales representative regarding availability of these parts. [+] feedback [+] feedback
cy7c106bn cy7c1006bn document #: 001-06429 rev. ** page 7 of 8 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. all product or company names mentioned in this docum ent may be the trademarks of their respective holders. package diagrams min. max. pin 1 id 0.291 0.300 0.050 typ. 0.007 0.013 0.330 0.350 0.120 0.140 0.025 min. 0.262 0.272 0.697 0.713 0.013 0.019 0.014 0.020 0.032 0.026 a a detail external lead design option 1 option 2 1 14 15 28 0.004 seating plane note : 1. jedec std ref mo088 2. body length dimension does not include mold protrusion/end flash mold protrusion/end flash shall not exceed 0.006 in (0.152 mm) per side 3. dimensions in inches 51-85031-*c 28-pin (300-mil) molded soj (51-85031) pin 1 i.d .435 .395 .445 .405 .128 .148 .360 .380 .026 .015 .032 .020 dimensions in inches min. max. .025 min. .007 .013 .050 typ. .720 .730 1 14 15 28 0.004 seating plane 51-85032.*b 28-lead (400-mil) molded soj (51-85032) [+] feedback [+] feedback
cy7c106bn cy7c1006bn document #: 001-06429 rev. ** page 8 of 8 document history page document title: cy7c106bn/cy7c1006bn 256k x 4 static ram document number: 001-06429 rev. ecn no. issue date orig. of change description of change ** 423847 see ecn nxr new data sheet [+] feedback [+] feedback
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